Weevaluate a Series of Three Progressively More Aggressive Routing-table Cache Designs and Demonstrate That the Incorporation of Hardware Caches into Internet Processors, Combined with Efficient Caching Algorithms Can Significantly

As a result of the exploding bandwidth demand from the Internet, network router and switch designers are designing and fabricating a growing number of microchips specifically for networking devices rather than traditional computing applications. In particular, a new breed of microprocessors, called Internet processors, has emerged that is designed to efficiently execute network protocols on various types of internetworking devices including switches, routers, and application-level gateways. One of the main tasks on the critical path of packet processing is route lookup. The routing lookup problem is equivalent to finding the longest prefix of a packet’s destination address in a table of address prefixes. Although, efficient algorithms to solve this problem exist, the architecture-level research question is how to execute them at wire speed. For example, if the router’s performance target is 10 million packets per second, the perpacket processing, including longest prefix match, should be completed within 100 ns. While router designers have made many attempts to build specialized hardware for clever packet routing and filtering algorithms, in this work we chose a time-tested architectural idea, caching, to attack this problem. This is based on the belief that there is sufficient locality in the packet stream for reusing routing computation results. However, caching alone is not sufficient due to less locality in packet-address streams than the instructionand data-reference streams in program execution. Given caches of a fixed configuration, the only way to improve the cache performance is to increase their effective coverage of the Internet protocol (IP) address space, that is, each cache entry must cover a larger portion of the IP address space. Toward this end, our work develops a novel address-range-merging technique by exploiting the limited number of outcomes for routing table lookup (the number of output interfaces in a network device) regardless of the size of the IP address space. Our simulation results demonstrate that address-range merging improves the caching efficiency by a factor of five over generic IP host-address caching, in terms of average routing tablelookup time.